1. Field of the Invention
This invention relates to a thin-film semiconductor device and a method of fabricating the same. More particularly, the invention relates to a thin-film semiconductor device comprising memory cells each consisting of a capacitor and a switching transistor connected to the capacitor, wherein the switching transistor is a thin-film transistor (hereinafter abbreviated as TFT); and, to a method of fabricating such a thin-film semiconductor device.
2. Description of the Prior Art
In recent years, the capacity of memory that can be stored on a single chip of semiconductor has been increasing by a factor of four approximately every three years, and the memory cell size has been shrinking. However, as for the basic memory cell structure in dynamic random access memories (DRAMs), the same one-transistor and one-capacitor configuration initially employed in 4-kilobit DRAMs has been in use over eight generations, and are currently used in 64-megabit DRAMs. In the meantime, the capacitor structure has been changed from a planar type to a trench type and to a stacked type. The type of insulating film has also been changed from the initial silicon oxide film to the most recent ONO (silicon oxide-nitride-oxide) film. With respect to the switching transistor, however, the only way to cope with the miniaturization of memory cells has been to reduce the size of the MOSFET whose channel is formed in a singlecrystalline substrate.
An example of the above prior art semiconductor device will now be described with reference to the accompanying drawing. FIG. 5 shows a cross sectional view of a memory cell in a prior art stacked capacitor type DRAM. As shown in FIG. 5, the capacitor comprises charge storage electrodes (storage nodes) 31a and 31b, a fixed potential application electrode (cell plate) 32, and a dielectric film 33 sandwiched between the electrodes 31a, 31b, and 32. Charge is stored on the capacitor. A switching MOSFET 34 comprises such elements as an impurity diffusion regions (source/drain regions) 37 formed at the surface of an semiconductor substrate 80 and a word line 35 that acts as the gate electrode of the switching MOSFET 34. The word line 35 is covered with silicon oxide film 82. The switching MOSFET 34 and the capacitor are covered with a silicon oxide film 83. A bit line 36 for charging the capacitor is formed on the silicon oxide film 83 so as to contact one of the impurity diffusion regions 37.
In the above configured semiconductor device, the switching MOSFET 34 is turned on by applying a voltage to the gate electrode 35 thereof, which in turn causes charges stored in the storage nodes 31a, 31b to flow through the impurity diffusion regions 37 and a channel region of the switching MOSFET 34 to the bit line 36, thereby enabling the information to be written into and read out of the capacitor. (See, for example, T. Ema et at., "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs", IEDM Dig. of Tech. Papers (1988), p.592.)
Another three-dimensional transistor structure designed for higher packing density is a surrounding gate transistor (SGT) such as is shown in FIGS. 7A and 7B. In the SGT, a word line 35 and a cell plate electrode 32 are wound around a silicon pillar 71 (formed by etching a surface of a silicon substrate 80), thereby forming a vertical transistor 34 and a capacitor. The capacitor comprises a storage node 37b formed in the surface region of the silicon pillar 71, a dielectric film 33 formed on the storage node 37b, and the cell plate electrode 32 formed on the storage node 37b. (See, for example, K. Sunouchi et at., "A Surrounding Gate Transistor (SGT) Cell for 64/256 Mbit DRAMs", IEDM Dig. of Tech. Papers (1989), pp.23-26.) As is shown in FIGS. 7A and 7B, a bit line 36 is connected to an impurity diffusion region 37a at the upper end of the silicon pillar 71. According to the above configuration, the gate length of the switching MOSFET 34 can be determined by the height of the silicon pillar 71, independently of device miniaturization in lateral directions.
In terms of integration, one cell requires one word line, a 1/2 bit line, one storage electrode contact, and a 1/2 bit line contact; the areas of these elements plus the process margins determine the minimum cell size. Therefore, for further miniaturization, these areas must be further reduced. For cell miniaturization, it is also necessary to reduce the gate length of the switching MOSFET, that is, the word line width. This dimension cannot be determined by miniature processing techniques alone, but degradation in characteristics such as channel leakage currents and hot carriers must also be taken into consideration to determine this dimension.
In the above mentioned configuration of FIG. 5, the storage electrodes are coupled to the impurity diffusion regions 37 formed at the substrate surface and the substrate 80 is usually held at a negative potential of -2 to -3 Volts to prevent the substrate from becoming unstable due to the pulse operation of the transistor. As a result, there is a problem in that the junction leakage increases and occupies a dominant proportion in the total leakage of the cell capacitor, the junction leakage thus determining the retention characteristic of the capacitor. The prior art semiconductor device has the further problem that the minority carriers dissociated because of the alpha particles injected into the substrate 80 are collected by the storage electrodes 31a and 31b, thereby causing the capacitor to discharge and resulting in soft errors.
In the surrounding gate transistor (SGT) illustrated in FIGS. 7A and 7B, since the bit line contact can be formed on the upper end (the impurity diffusion region 37a) of the silicon pillar 71, there is no such problem as is described above in terms of integration. However, this structure cannot be used for a stacked capacitor cell. Furthermore, since the impurity diffusion region in the substrate is also used as the storage node 37b, the junction leakage and alpha particles present greater problems than in the case of the stacked capacity cell shown in FIG. 5.